99精品在线观看-99精品在线免费观看-99精品在线视频观看-99精品这里只有精品高清视频-99九九精品国产高清自在线

x

全新Tensilica DPU系列產品提供10 GigaMAC/s DSP性能

2009-11-03 14:53:30 本站原創(chuàng)
點擊關注->創(chuàng)芯網(wǎng)公眾號,后臺告知EETOP論壇用戶名,獎勵200信元

Xtensa LX3 Customizable Dataplane Cores Tailored for High Performance DSP

SANTA CLARA, CA--(Marketwire - November 02, 2009) - Tensilica,® Inc. today introduced the Xtensa® LX3 high-performance dataplane processor (DPU) core optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers the industry's widest range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse.

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm(2) and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm(2) (post place-and-route 45GS) and consuming just 170 mW (including leakage).

The Xtensa LX3 DPU has been fine-tuned with optimized scripts for the latest generation of EDA tools, to deliver even better speed-power-area results than the predecessor Xtensa LX2 cores. When comparing functionally equivalent configurations of the Xtensa LX3 DPU versus the prior generation Xtensa LX2 DPU, the new Xtensa LX3 processor delivers up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power using identical process technologies and libraries.

"The Xtensa LX3 processor, Tensilica's flagship product, provides significant speed and power improvements to enable efficient digital signal processing and control processing in SOC or mixed signal devices," stated Jack Guedj, Tensilica's president and CEO. "We've invested heavily in our DPU technology to make it smaller, easier to use, and up to 20 percent faster, providing designers with the performance levels and connectivity expected from custom RTL blocks along with the programmability and debug benefits of conventional processors. And since Xtensa LX3 cores are pre-verified modules, it significantly reduces design risks for dataplane design compared to traditional custom hardware RTL design approaches."

Broadest Choice of DSP Options

The Xtensa LX3 DPU offers a wide array of pre-verified DSP options. Of course, designers can create their own DSP functionality using Tensilica's highly automated extensibility, but these pre-verified options speed up SOC time to market. The options include:

--  ConnX D2 DSP -- a new 16-bit dual-MAC SIMD (single instruction multiple data) DSP for communications, announced August 24, 2009
--  ConnX Vectra LX DSP -- an updated 16-bit quad-MAC SIMD DSP for communications (with new option for single load/store unit)
--  HiFi 2 audio DSP -- the most widely licensed audio DSP on the market today, a 24-bit, dual-MAC audio processor
--  A 32-bit IEEE-754 compliant single-precision floating point unit
--  A new 64-bit IEEE-754 compliant double precision floating point accelerator.
   
Easy System Integration

The Xtensa LX3 DPU was designed with multi-function, multi-core SOC designs in mind. Designers can easily connect the Xtensa LX3 DPU to the other elements of their SOC design in a variety of both traditional processor-centric and RTL-centric styles.

Using a standard 32-bit, 64-bit or 128-bit system bus, Tensilica offers support for AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks.

However, designers also can bypass the system bus altogether in order to achieve much higher input/output throughput and seamless integration with RTL via customizable Ports and Queues. These Ports and Queues let designers connect directly to RTL, allowing huge amounts of data to be transferred on each cycle without the need for separate load/store operations on the processor. For memory lookups, designers can connect lookup and scratchpad RAMs, as well as other long-latency hardware computation units, directly to the Xtensa DPU.

Performance Leadership Extended

Tensilica's Xtensa DPUs are the lowest power, highest performance licensable cores on the market based on previous industry standard benchmarks (see http://www.tensilica.com/products/xtensa-customizable/xtensa-lx2/benchmarks.htm) that are still not equaled by the competition.

Availability

The Xtensa LX3 customizable DPU is available now.

關鍵詞:

  • EETOP 官方微信

  • 創(chuàng)芯大講堂 在線教育

  • 半導體創(chuàng)芯網(wǎng) 快訊

全部評論

主站蜘蛛池模板: 国产合集福利视频在线视频| 黑人激情视频| 日韩视频亚洲| 2021年韩国r级理论片在线观看| 日韩一区二区三区四区| 成 人 免 费 黄 色| 欧美高清夜夜片a| 国产菲菲视频在线观看| 韩国成人在线视频| 国产成人综合久久综合| 久久久国产精品免费看| 亚洲高清综合| 中国xxxxxxxxx孕交| 一级黄色毛片免费看| 日韩毛片免费视频| 亚洲精品二区| 任你操精品| 欧美大尺度交性视频| 国产日本亚洲| 国产麻豆精品一区二区| 热re91久久精品国产91热| 91视频网| 成人午夜视频在线观看| 国产美女亚洲精品久久久综合91| 麻豆视传媒短视频网站-欢迎您| 三级午夜宅宅伦不卡在线| 亚洲国产欧美在线| 宅男69免费永久网站| 99精彩免费观看| 一级特黄aaa大片在| 久久欧美精品欧美久久欧美| 日本免费人成黄页在线观看视频| 加勒比一道本综合| 亚洲精品一区亚洲精品| 成人自拍小视频| 成人做爰全过程免费的叫床看视频 | 国产福利微拍精品一区二区| 精品欧美一区二区在线看片| 久久精品爱国产免费久久| 久久中文字幕久久久久91| 看片视频在线观看|